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SG6741 -- Highly Integrated Green-Mode PWM Controller
October 2008
SG6741 Highly Integrated Green-Mode PWM Controller
Features
High-Voltage Startup Low Operating Current: 4mA Linearly Decreasing PWM Frequency to 22kHz Frequency Hopping to Reduce EMI Emission Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Leading-Edge Blanking Synchronized Slope Compensation Gate Output Maximum Voltage Clamp: 18V VDD Over-Voltage Protection (Auto Restart) VDD Under-Voltage Lockout (UVLO) Internal Open-Loop Protection Constant Power Limit (Full AC Input Range)
Description
The highly integrated SG6741 PWM controller provides several features to enhance the performance of flyback converters. The highly integrated SG6741 series of PWM controllers provides several features to enhance the performance of flyback converters. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above 22KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is also eliminated. To further reduce power consumption, SG6741 is manufactured using the BiCMOS process, which allows an operating current of only 4mA. SG6741 integrates a frequency-hopping function that helps reduce EMI emission of a power supply with minimum line filters. Its built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary internal line compensation ensures constant output power limit over a wide range of AC input voltages, from 90VAC to 264VAC. SG6741 provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety when an open-loop or output short-circuit failure occurs. PWM output is disabled until VDD drops below the UVLO lower limit; then the controller starts again. As long as VDD exceeds about 26V, the internal OVP circuit is triggered. SG6741 is available in an 8-pin SOP package.
Applications
General-purpose switch-mode power supplies and flyback power converters, including: Power Adapters Open-Frame SMPS
Ordering Information
Part Number
SG6741SZ SG6741SY
Operating Temperature Range
-40 to +105C -40 to +105C
Package
8-Lead Small Outline Package (SOP) 8-Lead Small Outline Package (SOP)
Eco Status Packing Method
Green Green Tape & Reel Tape & Reel
For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
www.fairchildsemi.com 1
SG6741 -- Highly Integrated Green-Mode PWM Controller
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
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SG6741 -- Highly Integrated Green-Mode PWM Controller
Marking Information
T: S = SOP P: Z =Lead Free Null=regular package XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location F: Fairchild logo Z: Plant code X: 1 digit year code Y: 1 digit week code TT: 2 digits die run code T: Package type (S = SOP) P: Y=Green package M: Manufacture flow code
SG6741TP XXXXXXXXYWWV
Marking for SG6741SZ
ZXYTT 6741 TPM
Marking for SG6741SY
Figure 3. Top Mark
Pin Configuration
GND FB NC HV GATE VDD SENSE RI
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin #
1 2 3 4 5 6 7 8
Name
GND FB NC HV RI SENSE VDD GATE
Description
Ground. The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal on this pin and the current-sense signal on the SENSE pin. No connection. For startup, this pin is pulled high to the line input or bulk capacitor via resistors. A resistor connected from the RI pin to GND pin provides the SG6741 with a constant current source. This determines the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26K resistor (RI) results in a 65kHz center PWM frequency. Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the OVP trigger point. The totem-pole output driver. Soft driving waveform is implemented for improved EMI.
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
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SG6741 -- Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to the ground pin.
Symbol
VVDD VFB VSENSE VRI VHV PD JA TJ TSTG TL ESD DC Supply Voltage
(1, 2)
Parameter
FB Pin Input Voltage SENSE Pin Input Voltage RI Pin Input Voltage HV Pin Input Voltage Power Dissipation (TA50C) Thermal Resistance (Junction-to-Air) Operating Junction Temperature Storage Temperature Range Lead Temperature (Wave Soldering or IR, 10 Seconds) Electrostatic Discharge Capability, Human Body Model, JESD22-A114 Electrostatic Discharge Capability, Machine Model, JESD22-A115 All Pins Except HV Pin All Pins Except HV Pin
Min.
-0.3 -0.3 -0.3
Max.
30 7.0 7.0 7.0 500 400 141
Unit
V V V V V mW C/W C C C kV V
-40 -55
+125 +150 +260 4 200
Notes: 1. All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
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SG6741 -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V, TA=25C, unless otherwise noted.
Symbol VDD Section
VOP VDD-ON VDD-OFF IDD-ST IDD-OP IDD-OLP VTH-OLP VDD-OVP tD-VDDOVP
Parameter
Continuously Operating Voltage Start Threshold Voltage Minimum Operating Voltage Startup Current Operating Supply Current Internal Sink Current IDD-OLP off Voltage VDD Over-Voltage Protection VDD Over-Voltage Protection Debounce Time
Conditions
Min.
Typ.
Max.
22
Units
V V V A mA A V V s
15.5 9.5 VDD-ON - 0.16V VDD=15V, GATE Open VDD-OLP +0.1V 50 6.5 25 100
16.5 10.5 4 70 7.5 26 180
17.5 11.5 30 5 90 8.0 27 260
HV Section
IHV IHV-LC Supply Current from HV Pin Leakage Current After Startup VAC=90V (VDC=120V), VDD=10F HV=500V, VDD=VDDOFF+1V 2.0 1 20 mA
A
Oscillator Section
fOSC tHOP fOSC-G fDV fDT Frequency in Nominal Mode Hopping Period Green-Mode Frequency Frequency Variation vs. VDD Deviation Frequency Variation vs. Temperature Deviation VDD=11V to 22V TA=-40 to 105C 16 Center Frequency Hopping Range 62 3.7 65 4.2 4.4 18 21 5 5 68 4.7 KHz ms KHz % %
Continued on the following page...
PWM Frequency fOSC
fOSC-G
VFB-ZDC VFB-G
VFB-N
VFB
Figure 5. VFB vs. PWM Frequency
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
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SG6741 -- Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
VDD=15V, TA=25C, unless otherwise noted.
Symbol
Feedback Input Section AV ZFB VFB-OPEN VFB-OLP tD-OLP VFB-N VFB-G VFB-ZDC
Parameter
Input Voltage to Current-Sense Attenuation Input Impedance Output High Voltage FB Open-Loop Trigger Level Delay Time of FB Pin Open-Loop Protection Green-Mode Entry FB Voltage Green-Mode Ending FB Voltage Zero Duty-Cycle Input Voltage
Conditions
Min.
1/3.75 4
Typ.
1/3.20
Max. Units
1/2.75 7 V/V k V V ms V V V
FB Pin Open RI=26k
5.5 3.7 50 1.9 4.0 56 2.1 VFB-N0.5
4.3 62 2.3
VFB-G 0.25
VFB-G - VFB-G 0.20 0.10 12
Current-Sense Section ZSENSE VSTHFL VSTHVA tPD tLEB VS-SCP tD-SSCP Input Impedance Current Limit Flatten Threshold Voltage Current Limit Valley Threshold Voltage Delay to Output Leading-Edge Blanking Time Threshold Voltage for SENSE Short-Circuit Protection Delay Time for SENSE Short-Circuit Protection Maximum Duty Cycle Gate Low Voltage Gate High Voltage Gate Rising Time Gate Falling Time Gate Source Current Gate Output Clamping Voltage VDD=15V, IO=50mA VDD=12.5V, IO=50mA VDD=15V, CL=1nF VDD=15V, CL=1nF VDD=15V, GATE=6V VDD=22V 8 150 30 250 18 250 50 350 90 VSENSE<0.15V, RI=26k 275 VSTHFL-VSTHVA 0.87 0.30 K 0.93 0.38 200 425 V V ns ns V s 0.90 0.34 100 350 0.15 180
GATE Section DCYMAX VGATE-L VGATE-H tr tf IGATESOURCE
70
75
80 1.5
% V V ns ns mA V
VGATECLAMP
Notes: 3. When activated, the output is disabled and the latch is turned off. 4. The threshold temperature for enabling the output again and resetting the latch after OTP has been activated.
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
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SG6741 -- Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics
Operating Supply Current (IDD-OP) vs Temperature
25
5.0
20
4.0
15
IDD-OP (mA)
IDD-ST (A)
3.0
10
2.0
5
1.0
0 40 25 10 5 20 35 50 65 80 95 110 125
0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature ()
Temperature ()
Figure 6. Startup Current (IDD-ST) vs. Temperature
Start Threshold Voltage (VDD-ON) vs Temperature
20.0
Figure 7. Operation Supply Current (IDD-OP) vs. Temperature
Minimum Operating Voltage (VDD-OFF) vs Temperature
13.0
19.0
12.0
VDD-OFF (V)
-40 -25 -10 5 20 35 50 65 80 95 110 125
VDD-ON (V)
18.0 17.0
11.0
10.0
16.0
9.0
15.0
8.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature ()
Temperature ()
Figure 8. Start Threshold Voltage (VDD-ON) vs. Temperature
Supply current drawn from pin HV (IHV) vs Temperature
5.0
Figure 9. Minimum Operating Voltage (VDD-OFF) vs. Temperature
10
4.0
8
IHV (mA)
IHV-LC (A)
3.0
6
2.0
4
1.0
2
0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
0 40 25 10 5 20 35 50 65 80 95 110 125
Temperature ()
Te m pe ratur e ( )
Figure 10. Supply Current Drawn from HV Pin (IHV) vs. Temperature
70
Figure 11. HV Pin Leakage Current After Startup (IHV-LC) vs. Temperature
Maximum Duty Cycle (DCYMAX) vs Temperature
70.0
68
68.0
f OSC (kHz)
DCY (%) MAX
40 -25 -10 5 20 35 50 65 80 95 110 125
66
66.0
64
64.0
62
62.0
60
60.0 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature ()
Temperature ()
Figure 12. Frequency in Nominal Mode (fOSC) vs. Temperature
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3 7
Figure 13. Maximum Duty Cycle (DCYMAX) vs. Temperature
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SG6741 -- Highly Integrated Green-Mode PWM Controller
Functional Description
Startup Current
For startup, the HV pin is connected to the line input or bulk capacitor through an external resistor, RHV, which is recommended as 100K. Typical startup current drawn from pin HV is 2mA and it charges the hold-up capacitor through the resistor RHV. When the VDD capacitor level reaches VDD-ON, the startup current switches off. At that moment, the VDD capacitor only supplies the SG6741 to maintain the VDD before the auxiliary winding of the main transformer to carry on provide the operating current.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at 16.5V/10.5V. During startup, the hold-up capacitor must be charged to 16.5V through the startup resistor so that IC is enabled. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10.5V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup.
Operating Current
Operating current is around 4mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance.
Green-Mode Operation
The patented green-mode function provides an off-time modulation to reduce switching frequency in light-load and no-load conditions. The on time is limited for better abnormal or brownout protection. VFB, which is derived from the voltage feedback loop, is used as the reference. Once VFB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency, around 22KHz (RI=26K).
Gate Output / Soft Driving
The SG6741 BiCMOS output stage is a fast totem pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over-voltage. A soft driving waveform is implemented to minimize EMI.
Oscillator Operation
A resistor connected from the RI pin to the GND pin generates a constant current source for the controller. This current is used to determine the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26K resistor RI results in a corresponding 65KHz PWM frequency. The relationship between RI and the switching frequency is:
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. SG6741 inserts a synchronized positive-going ramp at every switching cycle.
fPWM
=
1690 (KHz) RI (K )
(1)
Constant Output Power Limit
When the SENSE voltage, across the sense resistor RS, reaches the threshold voltage around 0.9V, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current, proportional to tPD * VIN / LP. The delay is nearly constant, regardless of the input voltage VIN. Higher input voltage results in a larger additional current and the output power limit is also higher than that under low input line voltage. To compensate this variation for wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp signal and is fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs.
The range of the PWM oscillation frequency is designed as 47kHz ~ 109kHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized in SG6741 to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and VFB, the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP = (VFB-1.2)/3.2, the switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.85V for output power limit.
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
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SG6741 -- Highly Integrated Green-Mode PWM Controller
Functional Description (Continued)
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection has been built in to prevent damage due to abnormal conditions. Once the VDD voltage is over the VDD over-voltage protection voltage (VDD-OVP), and lasts for tD-VDDOVP, the PWM pulses is disabled until the VDD voltage drops below the UVLO, then starts up again. Over-voltage conditions are usually caused by open feedback loops.
Noise Immunity
Noise on the current sense or control signal may cause significant pulse width jitter, particularly in the continuous-conduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near to the SG6741, and increasing the power MO gate resistance improves performance.
Limited Power Control
The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, the supply voltage VDD begins decreasing. When VDD goes below the turn-off threshold (eg, 10.5V) the controller totally shuts down. VDD is charged up to the turn-on threshold voltage of 16V through the startup resistor until PWM output is restarted. This protection is activated as long as the overloading condition persists. This prevents the power supply from overheating.
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
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SG6741 -- Highly Integrated Green-Mode PWM Controller
Applications Information
2 BD1 2 4 2 CN1 1 2 3 1 3 CN1 L1 T1 4 VZ1 C1 C2 1 3 4 1 2 4 5 6 2 1 T2 8 3 + 3 C4 2 2 1 + C7 1 1 3 D2 7 + C8 1 3 D1 C3 C5 R1 Q1 1 L4 VO+ 2 2 L2 4 1 VO+ 1 2 R2 C6
2
VO2 R3 2 R4 1 3 D3 1 2 + U1 1 2 C12 3 4 GND FB NC HV SG6741 GATE VDD SENSE RI 8 7 6 5 R6 C10 R5 1 C9 2 R7 U2 R8 4 1 Q2
VO+
R9 R10 3 K2 C11 R U3 A R11
Figure 14. 60W Flyback 12V/5A Application Circuit
BOM
Designator
BD1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 D1 D2 D3 F1 L1 Q1
Part Type
BD 4A/600V XC 0.68F/300V XC 0.1F/300V YC 2200pF/Y1 EC 120F/400V CC 0.01F/500V CC 1000pF/100V EC 1000F/25V EC 470F/25V EC 22F/50V CC 470pF/50V CC 2200pF/50V CC 0.01F/50V Zener Diode 15V 1/2W (option) BYV95C FR103 FUSE 4A/250V Inductor (900H) STP20-100CT Q2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11
Designator
Part Type
MOS 7A/600V R 100K 1/2W R 47 1/4W R 100K 1/2W R 20 1/8W R 100 1/8W R 33K 1/8W R 0.3 2W R 680 1/8W R 4.7K 1/8W R 150K 1/8W R 39K 1/8W Thermistor TTC104 10mH 600H(PQ2620) IC SG6741 IC PC817 IC TL431 VZ 9G
THER1 T1 T2 U1 U2 U3 VZ1
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
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SG6741 -- Highly Integrated Green-Mode PWM Controller
Physical Dimensions
5.00 4.80 3.81
8 5
A
0.65
B
6.20 5.80
4.00 3.80
1 4
1.75
5.60
PIN ONE INDICATOR
(0.33)
1.27
0.25
M
CBA
1.27
LAND PATTERN RECOMMENDATION
0.25 0.10 1.75 MAX
C 0.10 0.51 0.33 0.50 x 45 0.25 C
SEE DETAIL A
0.25 0.19
OPTION A - BEVEL EDGE
R0.10 R0.10
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13
8 0 0.90 0.406
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 15. 8-Pin Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
www.fairchildsemi.com 11
SG6741 -- Highly Integrated Green-Mode PWM Controller
(c) 2008 Fairchild Semiconductor Corporation SG6741 * Rev. 1.3.3
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